The present invention relates to semiconductor devices and methods of forming the same, and more particularly, to scalable two transistor memory devices and methods of forming the same.
A dynamic random access memory (DRAM) device can be highly integrated in comparison with a static random access memory (SRAM) device. A DRAM device typically requires a periodic refresh in order to retain data stored in capacitors. Therefore, a typical DRAM consumes power even in a stand-by mode. On the other hand, non-volatile memory devices, such as flash memory devices, typically do not need to refresh memory cells in order to retain the stored data. However, a typical flash memory device takes a relatively long time to program and a tunneling oxide layer in the flash memory device may be damaged as erase and program operations are repeated.
Therefore, new memory cells having advantages of the DRAM device and the flash memory device have been studied. One such type of new memory cell is a scalable two-transistor memory (STTM) cell, as described in U.S. Pat. No. 5,952,692 to Nakazato et al. entitled “Memory Device With Improved Charge Storage Barrier Structure.” An STTM cell can provide high speed, low power consumption and high integration.
FIG. 1 is a cross-sectional view showing a unit cell of a conventional STTM device. Referring to FIG. 1, the unit cell of the memory device includes a planar transistor and a vertical transistor. The planar transistor includes a drain region 17d, a source region 17s and a storage node 5. The drain/source regions 17d and 17s are formed at a predetermined region of a semiconductor substrate 1, spaced apart from each other. The storage node 5 is disposed over a channel region between the drain/source regions 17d and 17s. The source/drain regions 17s and 17d are impurity-doped regions formed by implanting impurity ions into the semiconductor substrate 1. The drain region 17d corresponds to a bit line. The storage node 5 is electrically isolated. A gate insulation layer 3 is interposed between the storage node 5 and the channel region.
A multiple tunnel junction barrier pattern 12 and a data line 13 are formed on the storage node 5. The multiple tunnel junction barrier pattern 12 includes alternating semiconductor layers 7 and tunnel insulation layers 9. A top of the multiple tunnel junction barrier pattern 12 may be the tunnel insulation layer 9.
A data line 13 extends to electrically connect with a plurality of neighboring memory cells. The storage node 5, the multiple tunnel junction barrier pattern 12 and the data line 13 compose a multiple layer pattern 15. Sidewalls and an upper surface of the multiple layered pattern 15 are covered by a gate interlayer dielectric layer 19. A control line 21 is disposed on the gate interlayer dielectric layer 19 and crosses over the date line 13. The data line 13, the multiple tunnel junction barrier pattern 12, the storage node 5 and the control line 21 form the vertical transistor.
According to the conventional technology as described above, the source/drain regions 17s and 17d are impurity-doped regions. Thus, as size of the unit cell becomes decreased, punch through between the source/drain regions 17s and 17d may become more likely. That is, even though the unit cell may be reduced in size, properties, such as punch through between the source/drain regions 17s and 17d, may limit scalability.